Selected Projects
- Reliable Low-Latency and Low-Complexity Viterbi Architectures Benchmarked on ASIC and FPGA
- Hardware Implementation of Floyd-Steinberg Halftoning Algorithm
- Evaluation of Crosstalk Avoidance Coding Schemes
- Implementation of NoC Router / Switch
- System Design Project: Multi-Channel ADPCM CODEC (MCAC)
- Intel Xeon E5 v2 Architecture
- Design of DDR3 SDRAM Controller
- HAND SIGN INTERPRETER